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Fetch-decode-execute-plot

This is an unplugged resource to simulate the fetch-decode-execute cycle in a processor. It is a frantic starter activity aimed at students aged 17-18. The teacher acts as the computer memory, passing out instructions to the students. The students take on three different roles, fetcher, decoder and executer.  At...

Publication date:
2010 to date

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RISC vs CISC starter activity

This is quick starter activity for A-level students aged 17-18. The aim of the activity is to revise the key differences between RISC and CISC processors and to ensure students can explain which architecture should be used in a given situation.

Bernadette Malcolmson is the author of the resource.

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Publication date:
2010 to date

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